1) Field of the Invention
This invention relates generally to fabrication of in laid metal lines for semiconductor devices and more particularly to a method for patterning a seed layer that is used to selectively deposit metal in a damascene or dual damascene process.
2) Description of the Prior Art
Low resistivity metal such as aluminum and copper and their binary and ternary alloys have been widely explored as fine line interconnects in semiconductor manufacturing. Typical examples of fine line interconnect metal include Al.sub.x Cu.sub.y, ternary alloys Al--Pd--Cu, and Al--Pd--Nb and Al--Cu--Si and other similarly low resistivity metal based alloys. Emphasis on scaling down line width dimensions in very large scale integrated (VLSI) circuitry manufacture has led to reliability problems including inadequate isolating, electromigration, and planarization.
Damascene processes using metal filling vias and lines followed by chemical-mechanical polish (CMP) with various Al, Cu, and Cu-based alloys are a key element of wiring technologies for very large-scale system integration. Damascene and dual damascene processes are described C. Y. Chang, S. M. Sze, in ULSI Technology, by The McGraw-Hill Company, INC. copyright 1997, pp. 444-445.
A key part of the invention is the inventor's recognition of new problems--dishing 152 and residue 151 with electroplated line processes. See FIG. 6C. As the inventor's damascene and dual damascene processes have been implemented with soft metals (e.g., metals such as Al--Cu, Cu, alloys of Al, etc.) the inventor have found that the CMP process has caused a dishing problem 152 in the top surface of the metal lines. That is the CMP process removed more material in the center of the metal lines that at the edges thus causing an indentation or dishing problem. Preventing this dishing and completely removing Cu on oxide are the main object of this invention. Note that Cu on large areas of oxide are difficult to remove using chemical-mechanical polish (CMP).
FIG. 6A shows a top down view of a integrated circuit. FIGS. 6B and 6C are cross sectional views along axis 6B in FIG. 6A. Trenches 124 are formed in the insulating layer 20. The metal line patterns 150 are formed in the trenches 124. A seed/barrier layer 130 is formed on all of the top surface of the insulating layer 20. A metal layer 150 is deposited on the seed/barrier layer 130 preferably using an electro plating method. As shown in FIG. 6C, the inventor has found that when the metal layer 150 and seed/barrier layer 130 is chemical-mechanical polished, dishing 152 occurs. This dishing is worse over large pad areas 32. Also, the inventor has found that metal 150 and seed layer 130 form residues 151 in areas 151 (large areas of oxide) after the CMP as shown in FIG. 6C.
Therefore new methods are needed to overcome this dishing problem and residue problem.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,183,795 (Ting) shows a method for electroless of Copper on the bottom of a trench. However, the patent does not show the seed layer on the sidewalls of the damascene trench.
U.S. Pat. No. 5,055,425 (Leibovitz) Stacked solid via formation in integrated circuit systems--shows a Cu electroplating process.
U.S. Pat. No. 4,981,715 (Hirsch) Method of patterning electroless plated metal on a polymer substrate--discloses a method for patterning electroless plated metal. A substrate is first coated with a polymer suitable for complexing noble metal compounds. The substrate is then complexed with a noble metal compound, such as containing palladium, selectively irradiated to form the desired conductor pattern, and then etched so that the desired pattern remains. The substrate is subsequently placed in an electroless plating bath to form a metal pattern.
U.S. Pat. No. 5,262,354 (Cote) shows an interconnect process whereby the top metal layer is CMPed.
U.S. Pat. No. 5,595,937 (Mikagi) shows a method of forming Cu interconnect by MOCVD.
Dubin, Selective Electroless Ni Deposition On A TiW Underlayer For Integrated Circuit Fabrication, Thin Solid Films, 226 (1993) pp. 87 to 93, shows a method of forming a seed layer on the trench bottom and sidewalls using a PR process.